A need for low power integrated circuits, in part, has been driven by a concern for device reliability at high operating frequency and thin gate oxide as well as a desire to significantly improve battery life for portable applications. The lowering of the integrated circuit supply voltage levels has been an important vehicle for power reduction along with reductions in chip size. However, a need for higher functional integration on chips, such as adding both read/write cache memory and memory controllers on microprocessor units (MPUs), results in larger chips with large on-chip signal lines for data and logic. This trend towards integration limits the power savings realized through high local device packing density and lower supply voltages.
An increasing number and size of signal lines results in higher device power consumption from the charging and discharging of the signal lines. The amount of current required to charge a signal line from logic low to logic high is proportional to the capacitance of the line and the voltage between the high and low logic levels. An increase in the physical dimensions of the signal line results in a larger line capacitance and higher power consumption. With more and longer signal lines being used, the problem of signal line power consumption becomes apparent.